Semiconductor device manufacturers are migrating toward the use of high dielectric constant (e.g., high-k) gate dielectric, instead of the commonly used gate oxide. Metal gates, instead of polysilicon gates, are typically used to obtain the maximum benefit of using a high-k gate dielectric since a metal gate permits a better performance since it eliminates the voltage drop at the gate dielectric interface. In addition, metal gates enable optimization of the work function between the gate, gate dielectric, and substrate. Many integration schemes use a damascene replacement gate process to form such metal gates.
For example, a damascene gate is commonly formed by first depositing a high-k gate dielectric on a substrate, depositing polysilicon on the gate dielectric, and patterning the polysilicon into a dummy gate (e.g., mandrel). Any desired spacers, implants (e.g., source, drain, halo, etc.), silicides, etc., are formed before an interlevel dielectric layer (ILD) is formed over the top of the structure. The ILD is then recessed down to the top of the polysilicon and the polysilicon dummy gate is stripped away, leaving a gate trench in the ILD. Metal is then deposited into the gate trench, resulting in a metal gate formed on a high-k gate dielectric.
Transistors having relatively tall metal gates may suffer from parasitic capacitance. However, it is not a trivial matter to simply reduce the height of the dummy polysilicon gate in order to achieve a shorter metal gate. This is because aggressively scaling (e.g., reducing) the polysilicon height may also affect other devices that are fabricated using the same polysilicon as the dummy gate. Particularly, reducing the polysilicon height can detrimentally affect polysilicon resistors and e-fuses.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.